Topological Qubits: A Different Way to Build a Quantum Computer

Earlier posts here covered five qubit platforms: superconducting, trapped ion, photonic, neutral atom, and silicon spin. Each one answers the same question differently: how do you isolate a quantum system long enough to do useful computation? Topological qubits are the sixth approach, and the most contested. They exist at the intersection of materials science, condensed matter physics, and a twenty-year bet by Microsoft that the rest of the field is solving the wrong problem.

Every qubit in a quantum computer is fragile. Superconducting qubits, the kind Google and IBM use, operate near absolute zero and still lose coherence in microseconds. Gate error rates run between 0.1% and 1%, which sounds small until you consider that a useful fault-tolerant quantum computer may need error rates below one in a million. The industry has spent years stacking error correction on top of error correction, adding physical qubits to protect logical ones.

Topological qubits take a different approach. Instead of fighting noise with redundancy, they aim to make the qubit itself resistant to local disturbances. The physics relies on Majorana zero modes, exotic quasiparticles that store quantum information non-locally across two spatially separated points. Because the information is spread out, a local disturbance at one point cannot corrupt the qubit on its own. Topology, the branch of math that describes properties preserved under continuous deformation, gives the qubit its protection. You would have to disturb both ends of the system simultaneously to flip the state, which is far less likely than a single-point noise event.

Microsoft has pursued this path for nearly two decades through its Station Q research group. In February 2025, the company announced Majorana 1, described as the world's first quantum processor built on a topological core architecture. The chip used indium arsenide and aluminum, a hybrid superconductor-semiconductor platform. The research appeared in Nature in February 2025. The announcement drew immediate scrutiny. Independent researchers questioned the Topological Gap Protocol Microsoft uses to confirm the presence of Majorana modes, a University of St Andrews physicist published a challenge to its validity in March 2025, and Scientific American noted that Microsoft had previously retracted a high-profile Nature paper in 2021 after outside experts found the data could have come from material imperfections rather than topological qubits.

On June 2, 2026, Microsoft announced Majorana 2 at its Build 2026 conference. The new chip replaces aluminum with lead in the superconducting material stack and redesigns the semiconductor structure. Microsoft reports a mean qubit lifetime of 20 seconds, with some measurements exceeding one minute. That is a claimed 1,000-fold improvement over Majorana 1. Gate operations run at one microsecond, and the qubit footprint is 1/100th of a millimeter. The company now targets a commercially useful scalable quantum computer by 2029, moved up from a prior estimate of 2033. The materials iteration was accelerated with Microsoft Discovery, the company's agentic AI platform for scientific research.

The physics community's response has been consistent with the pattern from Majorana 1. Outside experts say the topological approach still lacks sufficient independent verification. The 20-second coherence time is striking if accurate, since superconducting qubits typically decohere in around 100 microseconds. But coherence time alone does not confirm the topological mechanism Microsoft claims is responsible for it. The company has a history of bold announcements followed by retraction or significant revision, and that history shapes how the community reads each new result.

Compared to the five platforms covered in earlier posts, topological qubits occupy a unique position. Superconducting qubits and silicon spin qubits are fabricated systems with well-characterized error mechanisms. Trapped ions and neutral atoms offer long coherence times but slow gates. Photonic qubits avoid decoherence but struggle with deterministic interactions. Topological qubits, if the physics holds, would offer built-in error protection that reduces the overhead for fault tolerance substantially. IBM's Condor chip reached 1,121 superconducting qubits in 2023. Microsoft is betting that the right number is not more physical qubits but better ones, and that topological protection is how you get there.

Whether Majorana 2 represents genuine progress or another contested milestone, Microsoft is the only major commercial player publishing peer-reviewed claims on topological qubit architecture. The debate in the physics community is real, the skepticism is well-founded, and the potential, if the approach works, remains significant. If you want the background on the other five platforms before going deeper on this one, the earlier posts are linked at the top of this page.

QuEra's Room-Temperature Bet

In March, Google Quantum AI announced it was adding neutral atoms to its superconducting program. I wrote about that move earlier this year. The Google post noted continued collaboration with QuEra Computing, the MIT and Harvard spinout whose researchers built much of the foundational methodology. A new interview with QuEra's chief commercial officer Yuval Boger at Embedded.com fills in what that methodology looks like in a running system.

Most quantum computers sit inside dilution refrigerators cooled below 0.01 Kelvin, colder than deep space. That hardware is expensive, heavy, and energy-hungry. A typical installation can draw tens of megawatts once you factor in the cooling plant. Superconducting qubits need it because they lose coherence at any meaningful thermal noise.

Neutral-atom machines skip the refrigerator entirely. QuEra traps individual rubidium atoms with laser-based optical tweezers, then drives them between energy states with more lasers. The atoms themselves get cooled to near absolute zero in a vacuum chamber, but the room housing the machine stays at normal office temperature. Boger says QuEra's systems run on a little over 10 kilowatts, roughly what five hair dryers pull.

The footprint matches the power draw. A few hundred laser-trapped atoms fit in an area smaller than a square millimeter. The complete control system fits in a lab or data center with no cryogenic plumbing. Scaling up means splitting the laser into more beams, not adding more refrigerators. QuEra's Aquila processor runs 256 qubits today, accessible through Amazon Braket.

Error correction remains the hard engineering problem; Boger was blunt about that. But the power and footprint argument is already settled. Google running both platforms is the tell. Neutral atoms are no longer a research curiosity.

The Quantum Security Race: Software vs. Hardware

I wrote about quantum computing's threat to encryption back in December. This post goes deeper on the two primary paths to Post-Quantum Cryptography (PQC): software and hardware.

Encryption protects everything: your bank transactions, your medical records, your company’s intellectual property, and the communications infrastructure that governments and militaries depend on. All of it rests on mathematical problems that classical computers cannot solve in any practical timeframe. Quantum computers change that equation. They do not simply run faster than classical machines; they operate on fundamentally different principles that make certain hard math problems trivial. The encryption standards that have secured the internet for decades, RSA and ECC, will not survive contact with a sufficiently powerful quantum computer. The question is not whether this happens, but when. Most experts put that date around 2035. The problem is that replacing encryption is not like patching software or upgrading a server. It requires identifying every system, device, protocol, and data store that relies on vulnerable cryptography, and migrating all of it to new standards. That process takes a decade or more even when organizations start immediately. Most have not started. The window to act in an orderly, cost-effective way is open now, but it will not stay open.

Quantum computing will break widely used encryption. Experts put the timeline at around 2035, when quantum machines will likely have the power to crack RSA and ECC. The threat does not wait until then. Harvest Now, Decrypt Later (HNDL) attacks are happening now: adversaries intercept and store encrypted data today, betting they can decrypt it once quantum hardware matures.

To understand the stakes, it helps to know what RSA and ECC actually are. RSA (Rivest-Shamir-Adleman, named for its three MIT inventors in 1977) is the encryption standard that secures most of the internet today, including HTTPS, email, and VPNs. Its security rests on a simple fact: factoring the product of two very large prime numbers is computationally impractical for classical computers. A quantum computer running Shor’s algorithm eliminates that protection entirely. ECC, Elliptic Curve Cryptography, is a more efficient alternative that provides equivalent security to RSA with much smaller key sizes. It is widely used in mobile devices, payment systems, and digital certificates precisely because it is lightweight. Its security depends on the difficulty of the elliptic curve discrete logarithm problem, which Shor’s algorithm also breaks. Both are public-key cryptography systems, meaning they underpin the key exchange that makes encrypted communication possible in the first place. When quantum computers can crack them, the foundation of modern digital security fails.

Organizations need to move to Post-Quantum Cryptography (PQC). Two paths exist: software and hardware.

Software-based PQC means implementing NIST-selected algorithms, like CRYSTALS-Kyber (now standardized as ML-KEM under FIPS 203), at the application or OS layer. These algorithms rely on math that is computationally infeasible for classical and quantum machines alike. Among the top 1,000 websites, PQC support averages just 21.9%, dropping to 8.4% for the top 100,000, and only 3% of banking websites currently support it. The practical management approach is “crypto agility”, a modular architecture that lets you swap algorithms as standards evolve without rebuilding from scratch.

Software has limits. It can be too power-hungry for constrained environments, which is where hardware-based PQC comes in. Embedding cryptographic algorithms directly into silicon is faster and more energy-efficient. It matters most for the roughly 20 billion IoT devices deployed worldwide, many of which cannot run complex PQC algorithms in software. SEALSQ launched the QS7001 in late 2025, the first chip to embed NIST-standardized PQC algorithms directly at the hardware level. Samsung developed the S3SSE2A, its own hardware PQC security chip targeting IoT devices and industrial sensors. (Click table below to enlarge)

The transition math is there but major cryptographic migrations typically take more than a decade. The Data Encryption Standard (DES), adopted by the US government in 1977, was the dominant symmetric encryption algorithm for two decades. By the late 1990s it was demonstrably breakable, and NIST ran a competition to replace it. The winner, the Advanced Encryption Standard (AES), was standardized in 2001. Despite DES being publicly compromised, the full industry migration from DES to AES took roughly 16 years. The same pattern held for cryptographic hash functions: retiring the MD family in favor of the more secure SHA family took about 10 years even with clear technical justification. PQC is a more complex transition than either of those, touching more layers of the stack, more device types, and more legacy infrastructure.

The White House estimates the federal government will spend $7.1 billion on PQC migration between 2025 and 2035. Software and hardware solutions are not competing; they address different constraints in the same stack.

Google Quantum AI Expands to Neutral Atoms. I’ve Covered Both Platforms. Here’s the Context.

Source: Building superconducting and neutral atom quantum computers | Google Quantum AI | March 24, 2026

Google Quantum AI announced last week that it is adding neutral atom computing to its existing superconducting program. I covered both platforms in my qubit series earlier this year, so this is a good moment to connect the dots.

I wrote about superconducting qubits in January and neutral atom qubits in February. Google’s announcement is a practical illustration of why both matter, and why no single platform has won.

Superconducting systems have scaled to circuits with millions of gate and measurement cycles, each running in about a microsecond. Neutral atom arrays have reached roughly 10,000 qubits, but their cycle times run in milliseconds. The tradeoff breaks cleanly along two axes: superconducting scales more readily in circuit depth; neutral atoms scale more readily in qubit count. Google is betting that running both in parallel gets to commercially useful hardware faster than doubling down on one.

Key tradeoffs between superconducting and neutral atom qubit platforms.

To lead the neutral atom effort, Google hired Dr. Adam Kaufman from JILA and NIST in Boulder, Colorado. He retains his CU Boulder faculty appointment. Boulder is a credible home for this work: it hosts the NSF Q-SEnSE Institute, the National Quantum Nanofab, and the U.S. EDA Quantum TechHub. Google also noted its continued collaboration with QuEra, the neutral atom startup whose researchers built much of the foundational methodology.

Google also said it expects commercially relevant quantum computers based on superconducting technology by the end of this decade. Adding neutral atoms to the portfolio is not a hedge on that timeline; it is a way to cover problem types that each architecture handles differently.

If you want the technical foundation for what Google announced, my January and February posts are a great place to start.

Writing Is How I Learn

Writing is how I learn. Not a side effect of learning, the mechanism itself. It's only taken me 60 years or so to realize. Yeah it took me a little longer than it should have to figure out, partly because my mother was an English teacher. Growing up with that in the house, writing felt like an assignment, something to be graded and corrected. I guess I avoided it for years.

Now I cannot imagine working without it.

The habit really started in college. I was never a yellow highlighter. I took detailed notes in class, then went back and rewrote them, filling in gaps, looking up anything I had not fully understood. I was not studying. I was writing my way to comprehension. I just did not recognize it as writing at the time.

Looking back at over 800 blog posts since 2005, I cannot identify a single topic I learned in school, at least not directly. Along the way I wrote five textbooks. Each one forced the same process at a longer scale: find the gaps, trace the logic, write until it holds. What came after was anything but familiar. But the foundation school set has mattered more than I appreciated at the time.

Circuit analysis taught me how to trace cause and effect through a system. Signals and systems gave me a way to think about information in motion. Mathematics gave me a tolerance for abstraction. Physics gave me an instinct for what is physically possible and what is not. None of those subjects mapped directly to telecommunications, networking, cybersecurity, AI, or quantum computing. But without them, I would have had nothing to connect the new ideas to. Every emerging technology I have written about made more sense because of something I learned in a classroom decades earlier, even when the connection was not obvious at first.

My first real test was the transition from the plain old telephone service network to internet protocol. POTS was settled territory: copper pairs, circuit switching, predictable behavior. IP emerged as none of those things. The protocols were still being written, the standards contested, and the people producing the documentation were often the same people building the systems. There was no textbook that had caught up. Writing about it forced me to work through the logic myself, trace the signal path, understand why packet switching broke the assumptions that circuit switching had held for a century. Reading alone would not have gotten me there.

Each technology that followed emerged the same way. Networking protocols solidified and cybersecurity emerged alongside them, then ahead of them. AI emerged from research labs into practice before most organizations knew what to do with it. Quantum computing is emerging now, still settling on its own vocabulary, its own benchmarks, its own honest assessment of what it can and cannot do. I came to each as an outsider working from preprints, conference proceedings, vendor white papers, and conversations with people who were themselves still figuring it out.

That turned out to be the ideal condition for writing. When there is no established explanation to defer to, you have to build your own. For me, the act of building it is where the learning happens.

Every draft reveals what I actually understand and what I have been skimming over. Missing causal links surface immediately. So do circular definitions I had mistaken for insight. Quantum is no different. I understood qubits loosely until I wrote a series on qubit technologies for a general audience. Six posts in, I understood the field in a way that a month of reading had not produced.

My mother would note that I came around eventually :)

This is pretty much how I learn. Researchers call it elaborative encoding: building understanding by reconstructing information in your own words rather than receiving it passively. The VARK model would place me in the read/write category, though writing as a cognitive tool goes beyond simple preference. It is the mechanism by which I connect new ideas to existing foundations.

Not everyone learns this way, and that is a really important point. Some people think through conversation. Others need to build something physical, draw a diagram, or hear an explanation out loud before it clicks. The method matters less than finding the one that works for you and committing to it. For me, writing is that method. It always has been, even when I did not want to admit it.

Writing also serves readers who learn differently. A well-constructed post gives the visual learner a structure to follow, the read/write learner direct access to the logic, and the reflective learner something to push back against. I write to learn, but if the post does its job, someone with a completely different learning style picks something useful out of it too. That possibility has kept me writing for 21 years.

If you work in a technical field and you are not writing, start. Pick something you half-understand and write until you fully do.

This past week that came full circle. Someone at the Quantum Supply Chain Accelerator site walkthrough at STCC Technology Park mentioned my quantum computing posts. It was an encouragement to keep writing.

AI Runs on GPUs - It Stalls on Pipes

Based on: Rebuilding The Foundation: Why AI Infrastructure Needs To Change  |  Will Eatherton, Cisco  |  March 17, 2026

Every AI infrastructure conversation eventually lands on power. Megawatts per rack, cooling costs, grid capacity, carbon footprint. The power story is real, but we can’t forget about bandwidth.

I’m an old telecom guy, having spent over 30 years in telecom and networking, including running National Science Foundation Centers of Excellence focused on communications infrastructure. Bandwidth constraints are not new. What's new is the scale and the speed at which AI workloads are exposing them.

A 200,000-GPU (Graphics Processing Unit) cluster can consume 435 MW (Megawatts) of critical IT power. Of that, 17 MW goes to optical transceivers alone, just to move data between chips. When you scale to a million GPUs, the transceivers by themselves consume roughly 180 MW. That's not a power problem. That's a data movement problem that shows up on the power bill.

Cisco's Will Eatherton made the case this week that the real bottleneck in AI infrastructure has shifted from compute to data movement. GPU procurement still dominates the conversation. Networking, storage, and security are where the constraints are actually forming.

Bandwidth

Training large models requires clusters of tens of thousands of GPUs exchanging data continuously. The industry has settled on 102.4 Tbps (Terabits per second) switching silicon as the baseline for serious deployments. Traditional pluggable transceivers hit a wall at 800G and 1.6T speeds. The DSP (Digital Signal Processor) in each transceiver consumes up to 30W per port; at 200G channels, electrical loss reaches roughly 22 dB (decibels) before the signal reaches fiber. Two approaches address this.

Linear-drive Pluggable Optics (LPO) removes the DSP and lets the host ASIC (Application-Specific Integrated Circuit) drive the optical module directly, cutting per-link power by up to 50%.

Co-Packaged Optics (CPO) goes further by integrating optical engines onto the switch package itself, dropping electrical loss to 4 dB and per-port power to 9W. CPO eliminates the transceiver and DSP entirely, embedding electronic-to-optical conversion onto the switch ASIC.

Nvidia's Quantum-X InfiniBand CPO switches, entering production in 2026, deliver 115 Tbps across 144 ports at 800G. Broadcom's Tomahawk 6 (TH6-Davisson) ships 102.4 Tbps with full CPO. IDTechEx projects the CPO market will grow at a 37% CAGR (Compound Annual Growth Rate), exceeding $20 billion by 2036.

Topology

Scale-up (NVLink within a rack) and scale-out (InfiniBand or Ethernet across a data center) are both approaching practical limits. The next phase, scale-across, federates compute across geographically distributed locations into a single pool. Telecom engineers solved a version of this problem decades ago with distributed switching and ATM (Asynchronous Transfer Mode) traffic engineering. AI adds a harder constraint: gradient synchronization across a WAN (Wide Area Network) requires low, symmetric latency that wide-area networks were not built to guarantee. It breaks the latency-symmetry assumption in standard collective communication libraries such as NCCL (Nvidia Collective Communications Library), requiring deep-buffer routing, topology-aware all-reduce algorithms, and control planes that make traffic decisions based on path characteristics, not just throughput.

Nvidia's Spectrum-X Ethernet CPO platform targets this scale-across problem, combining switching and routing in a single solution with deep buffer support and integrated in-network computing via SHARP (Scalable Hierarchical Aggregation and Reduction Protocol).

Figure 1. Scale-across WAN topology: two GPU clusters connected via deep-buffer routers across a WAN, with shared DPU/SmartNIC security enforcement.

Storage

AI training creates a mixed-access pattern: large sequential reads across petabytes of training data, burst checkpoint writes during fault recovery, and sustained KV-cache (Key-Value cache) write pressure as context windows grow. RDMA-based (Remote Direct Memory Access) protocols, including RoCE (RDMA over Converged Ethernet) and NVMe-oF (NVM Express over Fabrics), cut storage latency from milliseconds to microseconds. Idle GPUs cost the same as active ones. When ingestion starves GPUs of data or checkpoint bursts block training progress, accelerator cycles go idle. Storage has to be designed into the architecture from the start, not bolted on.

Security

Model weights represent hundreds of millions of dollars in training cost. Protecting them requires hardware-based trust, confidential computing, and network segmentation. SmartNICs (Smart Network Interface Cards) and DPUs (Data Processing Units) now enforce zero-trust policy at line rate, isolated from the host OS (Operating System), handling IP filtering, session tracking, and rate limiting without CPU (Central Processing Unit) involvement. Multi-tenant inference clusters must maintain customer separation while meeting latency SLAs (Service Level Agreements), adding another layer of security complexity that traditional perimeter models were not designed to handle.

Organizations that get interconnect, storage, and security right will have capacity that GPU-focused competitors cannot replicate from a single cluster. Those that don't will rent infrastructure from the ones that do.

Source: Cisco Blogs: Rebuilding The Foundation — Why AI Infrastructure Needs To Change

CPO Market Data: IDTechEx — Co-Packaged Optics (CPO) 2026-2036

Nvidia CPO Technical Detail: Nvidia Developer Blog — Scaling AI Factories with Co-Packaged Optics

CPO Technology Overview: EDN — Where Co-Packaged Optics Technology Stands in 2026