On September 22, IonQ reported a real-time error decoder that runs on one standard off-the-shelf CPU. Decoding is the classical half of quantum error correction, and it sets a speed limit on the quantum half. This post covers what the decoder does, the architecture it serves, and what the test did and did not show.
What a Decoder Does
An error-correcting code measures parity checks on the qubits every cycle. The results, called syndromes, do not reveal the stored data. They show where errors likely occurred. A classical decoder reads the syndrome stream, infers the most probable errors, and hands corrections back to the machine. Some logical operations wait on that answer before the program can continue, so a slow decoder stalls the quantum computer. IonQ describes this as the failure of conventional approaches, where the classical side gets overwhelmed and the quantum system has to pause. Streaming decoders address it by processing syndromes faster than they accumulate.
The Architecture It Serves
IonQ published its Walking Cat architecture in April as a full blueprint for a trapped-ion fault-tolerant computer, covering the compiler, error-correction protocols, micro-architecture, and decoder. It builds entirely on low-density parity-check (LDPC) codes. In the notation [[n, k, d]], n is physical qubits, k is logical qubits, and d is the code distance. The paper introduces a [[70, 6, 9]] code for fast logical gates and a [[102, 22, 9]] code that packs 22 logical qubits into each memory block.
The hardware is a quantum charge-coupled device (QCCD) chip. Electric fields shuttle ions between storage and interaction zones, which lets the chip implement the non-local connections LDPC codes need. A cat factory produces cat states that travel through the machine and get consumed by logical operations. Reservoirs of fresh ions replace qubits lost during operation. The paper's dense design reaches 110 logical qubits and about one million T gates per day with 2,514 physical qubits. Speed is the tradeoff: IonQ estimates a 30-bit Shor factoring run takes about 23 hours.
Trapped-ion cycles run slower than superconducting ones, so the decoder works on a millisecond-scale budget. The April paper described a streaming beam decoder that works on syndrome data in sliding windows to fit that budget.
Testing the Decoder at 408 Logical Qubits
The new paper, Real-time decoder for a MegaQuOp quantum computer using a single CPU, evaluates a dual-decoder architecture on benchmark circuits. The circuits simulate up to 408 logical qubits across 88 memory blocks and magic state factories, and they run more than 31.5 million operations. Under standard operational noise, the decoder added as little as 0.02% stretch time, meaning extra run time spent waiting on decoding. The simulation exceeds the 110 logical qubits in the April dense design.
IonQ says the result shows classical hardware overhead does not have to grow exponentially with logical qubits or circuit depth. That claim matters for scaling, because a decoder that needs more classical hardware with every added qubit would cap the machine size. The company's roadmap runs past 256 physical qubits toward thousands.
Limits of the Result
Every circuit was simulated. The figures come from IonQ's own paper and press release, and they reflect a standard noise model. Hardware adds its own error mix, including the ion loss the April architecture handles with reservoirs. Whether the decoder holds its 0.02% overhead on a running machine is a hardware question, and no device with 408 logical qubits exists to answer it.
For readers of Quantum from the Ground Up: this adds a CPU-based decoder alongside the NVIDIA decoder in Chapter 12, and a classical-side entry to IonQ's coverage in Chapter 6. The two decoders report different metrics, so no ranking follows. The Q-Day range in Chapter 13 stays where it is until decoder results come from hardware. This post will be incorporated into the next edition. The current edition is at gordostuff.com/p/quantum-from-ground-up-hardware.html.
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