Chapter 14 of Quantum from the Ground Up covers the hardware side of post-quantum cryptography, meaning new encryption methods designed to survive an attack from a future quantum computer. This week gave that a concrete data point. BTQ Technologies and Taiwan's Industrial Technology Research Institute validated the first phase of a chip architecture built specifically to run the new encryption standards in hardware instead of software.
Why Hardware Matters Here
Encryption, whether old or new, is math. A processor runs that math the same way it runs any other program: by fetching instructions and data from memory, doing the calculation, then writing the result back. Post-quantum encryption methods use larger keys and more complex math than the encryption in use today, so they demand more of that fetch-and-calculate cycle. Running them purely in software, on a general-purpose processor, is slower and draws more power. That is a real problem for a car's onboard computer, a factory sensor, or a battery-powered IoT device that cannot spare the extra milliseconds or milliwatts.
The fix is to build a dedicated piece of hardware that runs only the encryption math, wired directly for that job. That is what a chip architecture like QCIM is.
What QCIM Actually Does
QCIM stands for Quantum Compute-in-Memory. Despite the name, it does not involve quantum computing itself. It refers to where the calculation happens on the chip. In a standard chip layout, memory and the processor are separate blocks connected by a data bus, and every calculation means shuttling data back and forth across that bus. Compute-in-memory design instead performs the calculation inside or immediately next to the memory itself, cutting out most of that back-and-forth. Less movement means lower power draw and faster results, which is exactly what power-constrained devices need if they are going to run demanding post-quantum math.
BTQ built this particular version around three specific encryption standards published by NIST: FIPS 203, 204, and 205. These are the official post-quantum algorithms the US government has approved for general use, covering both encrypting data and verifying digital signatures. Any hardware built to accelerate post-quantum cryptography needs to run these three algorithms specifically, since they are what systems will actually be required to support going forward.
What Was Tested, and What It Showed
The test ran inside a TSMC 28-nanometer design environment. TSMC is the world's largest chip manufacturer, and 28-nanometer refers to the size of the transistors in the manufacturing process being simulated, an older and well-proven node rather than the cutting edge, which keeps early testing cheaper and more predictable. Inside that environment, researchers checked two things. First, whether the QCIM core could genuinely speed up FIPS 203, 204, and 205 operations. Second, whether it produced correct results while doing so, since a faster chip that gets the math wrong is worthless for security. Both held up under the demanding conditions BTQ and ITRI put it through. ITRI's Dr. Chih-Cheng Lu called it meaningful progress toward module-level integration, the next phase of the program, where the core gets built into a larger working system rather than tested on its own.
BTQ is not new to this work. The collaboration with ITRI traces back to 2022, and a companion program with South Korea's ICTK is aimed at a fully integrated, commercially deployable chipset built around the same core. BTQ has said it expects to ship QCIM test chips to customers and partners by the end of the year. The target applications read like a list of things you do not want to re-secure one device at a time later: military systems, industrial equipment, automotive platforms, IoT devices, and connected infrastructure generally, all of which stay in service for years and are hard to patch remotely.
What This Changes in the Book
Chapter 14 already covers hardware paths to PQC, citing the SEALSQ QS7001. QCIM adds a second, independently developed example aimed at the same FIPS standards, this time using compute-in-memory design. The next edition adds it alongside QS7001 and tracks the module-level integration phase BTQ and ITRI are moving into next.
QCIM is the third hardware entry in a pattern this blog has been tracking since December: SEALSQ's QS7001, covered in The Quantum Security Race: Software vs. Hardware, and STMicroelectronics' ST54M, covered in Government Sets New Deadline for Quantum-Safe Encryption. All three chips target the same FIPS 203/204/205 standards introduced in Quantum Computers Just Got Much Closer to Breaking Your Passwords, and all three exist because the federal migration deadlines covered in that June post do not leave software-only implementations enough runway.
This post will fold into the next edition of Quantum from the Ground Up, due September 1.
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